The present invention relates to the field of programmable logic devices and methods of operation thereof. More specifically, in one embodiment the invention provides an improved architecture for programmable logic devices.
Programmable logic devices (PLDs), sometimes referred to as PALs, PLAs, FPLAs, PLDs, EPLDs, EEPLDs, LCAs, and FPGAs, are well know integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices allow a user to electrically program standard, off-the-shelf logic elements to meet the users specific needs. See, for example, U.S. Pat. No. 4,617,479, incorporated herein by reference for all purposes. Such devices are currently represented by, for example, Altera's MAX.sup.R series of PLDs and FLEX.TM. series of PLDs. The former are described in, for example, the Altera Data Book, September 1991, incorporated herein by reference. The latter are described in, for example, U.S. Ser. No. 07/880,942, filed May 8, 1992, and incorporated herein by reference for all purposes.
While meeting with substantial success, such devices have also met with some limitations. For example, it is desirable to increase the number of possible and alternative interconnection schemes between logical elements of such devices. Further, as the complexity of the functions becomes greater, it may become necessary to partition multiple logic chips in a single package.
From the above it is seen that improved programmable logic devices and methods of operation thereof are desired.